View EM42BM1684RTC-5FE_5621258.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

em42bm1684rtc apr. 2012 1/23 www.eorex.com revision history revision 0.1 (jun. 2010) - first release. revision 0.2 (sep. 2010) - add 166mhz@2.5-3-3; 200mhz@3-3-3, page 2 - ac characteristics cl=2.5 & 3 for tac, page 10 revision 0.3 (apr. 2012) - add idd7:four bank interleaving with bl=4 operating current
em42bm1684rtc apr. 2012 2/23 www.eorex.com 512mb (8m 4bank 16) double data rate sdram features ? internal double-date-rate architecture with 2 accesses per clock cycle. ? vdd/vddq= 2.5v 0.2v ? 2.5v sstl-2 compatible i/o ? burst length (b/l) of 2, 4, 8 ? 2.5,3 clock read latency ? bi- directional, intermittent data strobe (dqs) ? all inputs except data and dm are sampled at the positive edge of the system clock. ? data mask (dm) for write data sequential & interleaved burst type available ? auto precharge option for each burst accesses ? dqs edge-aligned with data for read cycles ? dqs center-aligned with data for write cycles ? dll aligns dq/dqs transitions with clk transition ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms description the em42bm1684rtc is high speed synchronous graphic ram fabricated with ultra high performance cmos process containing 536,870,912 bits which organized as 8meg words x 4 banks by 16 bits. the 512mb ddr sdram uses double data rate architecture to accomplish high-speed operation. the data path internally pre-fe tches multiple bits and it transfers the data for both rising and falling edges of the system clock. it means the doubled data bandwidth can be achieved at the i/o pins. available packages: tsopii 66pin 400mil . ordering information part no organization max. freq package grade pb em42bm1684rtc-6f 32m x 16 166mhz @cl2.5-3-3 tsopii-66 commercial free em42bm1684rtc-5f 32m x 16 200mhz @cl3-3-3 tsopii-66 commercial free em42bm1684rtc-6fe 32m x 16 166mhz @cl2.5-3-3 tsopii-66 extended free EM42BM1684RTC-5FE 32m x 16 200mhz @cl3-3-3 tsopii-66 extended free
em42bm1684rtc apr. 2012 3/23 www.eorex.com parts naming rule * eorex reserves the right to change products or specification without notice.
em42bm1684rtc apr. 2012 4/23 www.eorex.com pin assignment 66pin tsop-ii
em42bm1684rtc apr. 2012 5/23 www.eorex.com pin description (simplified) pin name function 45,46 clk,/clk (system clock) clock input active on the positive rising edge except for dq and dm are active on both edge of the dqs. clk and /clk are differential clock inputs. 24 /cs (chip select) /cs enables the command decoder when?l? and disable the command decoder when ?h?. the new commands are over- looked when the command decoder is disabled but previous operation will still continue. 44 cke (clock enable) activates the clk when ?h? and deactivates when ?l?. when deactivate the clock, cke low signifies the power down or self refresh mode. 28~32,35~42 a0~a12 (address) row address (a0 to a12) and column address (ca0 to ca9) are multiplexed on the same pin. ca10 defines auto precharge at column address. 26, 27 ba0, ba1 (bank address) selects which bank is to be active. 23 /ras (row address strobe) latches row addresses on the positive rising edge of the clk with /ras ?l?. enables row access & pre-charge. 22 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 21 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 16/51 ldqs/udqs (data input/output) data inputs and outputs are synchronized with both edges of dqs. 20/47 ldm/udm (data input/output mask) dm controls data inputs. ldm corresponds to the data on dq0~dq7.udm corresponds to the data on dq8~dq15. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0~dq15 (data input/output) data inputs and outputs are multiplexed on the same pin. 1,18,33/ 34,48,66 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuits. 3, 9, 15, 55.61/ 6, 12, 52, 58,64 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. 14,17,19,25,43, 50,53 nc/rfu (no connection/reserved for future use) this pin is recommended to be left no connection on the device. 49 v ref (input) sstl-2 reference voltage for input buffer.
em42bm1684rtc apr. 2012 6/23 www.eorex.com absolute maximum rating symbol item rating units v in , v out input, output voltage -1 ~ +3.6 v v dd , v ddq power supply voltage -1 ~ +3.6 v commercial 0 ~ +70 t op operating temperature range extended -25 ~ +85 c t stg storage temperature range -55 ~ +150 c p d power dissipation 1.6 w i os short circuit current 50 ma note: caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended peri ods may affect device reliability. capacitance (v cc =2.5v, f=1mhz, t a =25c) symbol parameter min. typ. max. units c clk clock capacitance(clk,/clk) 2 - 3 pf c i input capacitance for cke, address, /cs, /ras, /cas, /we 2 - 3 pf c o dm,data&dqs input/output capacitance 4 - 5 pf recommended dc operating conditions (t a =-0c ~+70c) symbol parameter min. typ. max. units note v dd power supply voltage 2.3 - 2.7 v v ddq power supply voltage (for i/o buffer) 2.3 - 2.7 v v ref i/o reference voltage 0.49 v ddq - 0.51 v ddq v v tt i/o termination voltage v ref -0.04 - v ref +0.04 v v ih input logic high voltage v ref +0.15 - v ddq +0.3 v v il input logic low voltage -0.3 - v ref -0.15 v
em42bm1684rtc apr. 2012 7/23 www.eorex.com recommended dc operating conditions (v dd =2.5v0.2v, t a =0c ~ 70c) max. symbol parameter test conditions -5 -6 units i dd1 operating current (note 1) burst length=2, t rc t rc (min.), i ol =0ma, one bank active 120 80 ma i dd2p precharge standby current power down mode cke v il (max.), t ck =min 10 10 ma i dd2n precharge standby current (all banks idle) cke v il (min.), t ck =min, /cs v ih (min.) input signals are changed once per clock cycle 50 45 ma i dd3p active standby current (power down mode) cke v il (max.), t ck =min 30 25 ma i dd3n active standby current (non-power down mode) cke v ih (min.), t ck =min, /cs v ih (min.) input signals are changed once per clock cycle 60 50 ma read 100 85 i dd4 operating current (burst mode) (note 2) t ck t ck (min.), i ol =0ma, all banks active write 100 85 ma i dd5 refresh current (note 3) t rc t rfc (min.), all banks active 150 130 ma i dd6 self refresh current cke 0.2v 5 5 ma i dd7 operating current four bank linterleaving with bl=4 300 250 ma *all voltages referenced to vss. note 1: i dd1 depends on output loading and cycle rates . specified values are obtained with the output open . input signals are changed only one time during t ck (min. ) note 2: i dd4 depends on output loading and cycle rates . specified values are obtained with the output open . input signals are changed only one time during t ck (min. ) note 3: min. of t rfc (auto refresh row cycle times) is shown at ac characteristics.
em42bm1684rtc apr. 2012 8/23 www.eorex.com recommended dc operating conditions (continued) symbol parameter test conditions min. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v -2 +2 ua i ol output leakage current 0 v o v ddq , d out is disabled -5 +5 ua v oh high level output voltage i o =-16.8ma 1.95 - v v ol low level output voltage i o =+16.8ma - 0.35 v
em42bm1684rtc apr. 2012 9/23 www.eorex.com block diagram row add. buffer row decoder address register auto/ self refresh counter memory array s/ a & i/ o gating col. decoder col. add. buffer mode register set col add. counter burst counter dqm control data in data out dio a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 timing register clk cke /cs / ras / cas /we dm dm /clk dqs dqs receiver write fifo driver dqs generator dll clk, /clk clk, /clk
em42bm1684rtc apr. 2012 10/23 www.eorex.com ac operating test conditions (v dd =2.5v0.2v, t a =0c ~70c) ac operating test characteristics (v dd =2.5v0.2v, t a =0c ~70c) symbol -5 -6 parameter min. max. min. max. units t dqck dq output access from clk,/clk -0.7 0.7 -0.7 0.7 ns t dqsck dqs output access from clk,/clk -0.55 0.55 -0.6 0.6 ns t cl ,t ch cl low/high level width 0.45 0.55 0.45 0.55 t ck cl=3 5 10 - - t ck clock cycle time cl=2.5 - - 6 12 ns t dh ,t ds dq and dm hold/setup time 0.4 - 0.45 - ns t dipw dq and dm input pulse width for each input 1.75 - 1.75 - ns t hz ,t lz data out high/low impedance time from clk,/clk -0.7 0.7 -0.7 0.7 ns t dqsq dqs-dq skew for associated dq signal - 0.4 - 0.4 ns t dqss write command to first latching dqs transition 0.72 1.25 0.75 1.25 t ck t dsl ,t dsh dqs input valid window 0.35 - 0.35 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpres write preamble setup time 0 - 0 - ns t wpre write preamble 0.25 - 0.25 - t ck t wpst write postamble 0.4 0.6 0.4 0.6 t ck t ih ,t is address/control input hold/setup time (fast slew rate) 0.6 - 0.75 - ns t rpre read preamble 0.9 1.1 t ck
em42bm1684rtc apr. 2012 11/23 www.eorex.com ac operating test char acteristics (continued) (vdd=2.5v0.2v, ta=0c ~70c) -5 -6 symbol parameter min. max. min. max. units t rpst read postamble 0.4 0.6 0.4 0.6 t ck t ras active to precharge command period 40 70k 42 70k ns t rc active to active command period 55 - 60 - ns t rfc auto refresh row cycle time 70 - 72 - ns t rcd active to read or write delay 15 - 18 - ns t rp precharge command period 15 - 18 - ns t wr write recover time 15 - 15 - ns t rrd active bank a to b command period 10 - 12 - ns t ipw control & address input width 2.2 - 2.2 - ns t rap active to read with auto precharge command 15 - 18 - ns t rpre dqs read preamble 0.9 1.1 0.9 1.1 t ck t wtr internal write to read command delay 2 - 1 - t ck t xsnr exit self refresh to non-read command 75 - 75 - ns t xsrd exit self refresh to read command 200 - 200 - t ck t refi average periodic refresh interval - 7.8 - 7.8 us
em42bm1684rtc apr. 2012 12/23 www.eorex.com simplified state diagram
em42bm1684rtc apr. 2012 13/23 www.eorex.com 1. command truth table cke command symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a12~a0 ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre-charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre-charge writa h x l h l l v h v bank activate act h x l l h h v v v pre-charge select bank pre h x l l h l v l x pre-charge all banks pall h x l l h l x h x mode register set mrs h x l l l l op code extended mrs emrs h x l l l l op code h = high level, l = low level, x = high or low level (don't care), v = valid data input 2. cke truth table cke item command symbol n-1 n /cs /ras /cas /we addr. idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x - l h l h h h x self refresh self refresh exit - l h h x x x x idle power down entry - h l x x x x x power down power down exit - l h x x x x x h = high level, l = low level, x = high or low level (don't care)
em42bm1684rtc apr. 2012 14/23 www.eorex.com 3. operative command table current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l x ba/ca/a10 read/writ/bw illegal (note 1) idle l l h h ba/ra act bank active,latch ra l l h l ba, a10 pre/prea nop (note 3) l l l h x refa auto refresh (note 4) l l l l op-code, mode-add mrs mode register h x x x x desl nop l h h h x nop nop l h h l ba/ca/a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba/ca/a10 writ/writa begin write,latch ca, determine auto-precharge row active l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea precharge/precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term terminal burst read l h l h ba/ca/a10 read/reada terminate burst,latch ca, begin new read, determine auto-precharge l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst, prechare l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l h ba/ca/a10 read/reada terminate burst with dm=?h?,latch ca,begin read,determine auto-precharge (note 2) l h l l ba/ca/a10 writ/writa terminate burst,latch ca,begin new write, determine auto-precharge (note 2) l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst with dm=?h?, precharge l l l h x refa illegal write l l l l op-code, mrs illegal
em42bm1684rtc apr. 2012 15/23 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba/ca/a10 term illegal l h l x ba/ra read/write illegal (note 1) l l h h ba/a10 act illegal (note 1) l l h l x pre/prea illegal (note 1) l l l h x refa illegal read with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal write with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea nop(idle after t rp ) (note 3) l l l h x refa illegal pre-charging l l l l op-code, mode-add mrs illegal h x x x x desl nop(row active after t rcd ) l h h h x nop nop(row active after t rcd ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal row activating l l l l op-code, mode-add mrs illegal h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge
em42bm1684rtc apr. 2012 16/23 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l h ba/ca/a10 read illegal (note 1) write l h l l ba/ca/a10 writ/writa new write, determine ap l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal recovering l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/writ illegal l l h h ba/ra act illegal l l h l ba/a10 pre/prea nop(idle after t rp ) l l l h x refa illegal refreshing l l l l op-code, mode-add mrs illegal h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 1: illegal to bank in specified states; function may be legal in the bank indica ted by bank address (ba), depending on the state of that bank. note 2: must satisfy bus contention, bus turn ar ound, and/or write recovery requirements. note 3: nop to bank precharging or in idle st ate.may precharge bank indicated by ba. note 4: illegal of any bank is not idle.
em42bm1684rtc apr. 2012 17/23 www.eorex.com 4. command truth table for cke current state c ke /cs /r /c /w addr. action h x x x x x x invalid l h h x x x x exist self-refresh l h l h h h x exist self-refresh self refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self refresh) h x x x x x x invalid l h h x x x x exist power down both bank l h l h h h x exist power down precharge l h l h h l x illegal power down l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain power down) h h x x x x x refer to function true table h l h x x x x enter power down mode (note 3) h l l h h h x enter power down mode (note 3) h l l h h l x illegal all banks h l l h l x x illegal idle h l l l h h ra row active/bank active h l l l l h x enter self-refresh (note 3) h l l l l l op-code mode register access h l l l l l op-code special mode register access l x x x x x x refer to current state any state other than listed above h h x x x x x refer to command truth table h = high level, l = low level, x = high or low level (don't care) notes 1: after cke?s low to high transition to exist self refresh mode.and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. notes 2: cke low to high transition is asynchronous as if restarts internal clock. notes 3: power down and self refresh can be entered only from the idle state of all banks.
em42bm1684rtc apr. 2012 18/23 www.eorex.com the sequence of power- up and initialization the following sequence is required for power-up and initialization. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock (clk, clk), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll. (to issue ?dll enable? command, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a12 and ba1) 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of cl ock input is required to lock the dll after enabling dll.
em42bm1684rtc apr. 2012 19/23 www.eorex.com mode register definition mode register set the mode register stores the data for controlling the various operating modes of ddr sdram which contains addressing mode, burst length, /cas latency, test mode, dll reset and various vendor s specific opinions. the defaults value of the register is not defined, so the mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on /cs, /ras, /cas, /we and ba0 ( the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register. ) the state of the address pins a0-a12 in the same cycle as /cs, /ras, /cas, /we and ba0 going low is written in the mode register. two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0-a2, addressing mode uses a3, /cas latency (read latency from column address) uses a4-a6. a7 is used for test mode. a8 is used for ddr reset. a7 must be set to low for normal mrs operation.
em42bm1684rtc apr. 2012 20/23 www.eorex.com address input for mode register set bust length bt cas latency tm dll rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 1 1 reserve 0 1 1 2.5 1 0 1 reserve 0 0 1 reserve 1 1 0 3 0 1 0 reserve 1 0 0 reserve 0 0 0 reserve a4 a5 a6 cas latency 1 interleave 0 sequential a3 burst type 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 8 0 1 0 4 1 0 0 2 0 0 0 reserve a0 a1 a2 burst latency 1 yes 0 no a8 dll rest 1 test 0 normal a7 mode 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use bust length bt cas latency tm dll rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 1 1 reserve 0 1 1 2.5 1 0 1 reserve 0 0 1 reserve 1 1 0 3 0 1 0 reserve 1 0 0 reserve 0 0 0 reserve a4 a5 a6 cas latency 1 interleave 0 sequential a3 burst type 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 8 0 1 0 4 1 0 0 2 0 0 0 reserve a0 a1 a2 burst latency 1 yes 0 no a8 dll rest 1 test 0 normal a7 mode 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use
em42bm1684rtc apr. 2012 21/23 www.eorex.com burst type (a3) burst length a2 a1 a0 sequential addressing interleave addressing x x 0 0 1 0 1 2 x x 0 1 0 1 0 x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 *page length is a function of i/o organization and column addressing dll enable / disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disable the dll for the purpose of debug or evaluation ( upon existing self refresh mode, the dll is enable automatically. ) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength got all outputs is specified to be sstl-2, class ii. some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments.
em42bm1684rtc apr. 2012 22/23 www.eorex.com extended mode regi ster set ( emrs ) the extended mode register stores the data enabling or disabling dll. the value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling dll. the extended mode register is written by asserting low on /cs, /ras, /cas, /we and high on ba0 ( the ddr sdram should be in all bank precharge with cke already prior to writing into the extended mode register. ) the state of address pins a0-a10 and ba1 in the same cycle as /cs, /ras, /cas, and /we going low is written in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. high on ba0 is used for emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation. dll i/o 0 rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 half 0 full a1 i/o strength 1 disable 0 enable a0 dll enable 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use must be set to ?0? dll i/o 0 rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 half 0 full a1 i/o strength 1 disable 0 enable a0 dll enable 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use must be set to ?0?
em42bm1684rtc apr. 2012 23/23 www.eorex.com package description

▲Up To Search▲

Price & Availability of EM42BM1684RTC-5FE

	To Download EM42BM1684RTC-5FE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .